library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity left_shifter is
	generic (
		size		: in  positive
	);
	port (
		data		: in  std_logic_vector(size-1 downto 0);
		shift		: in  std_logic_vector(size-1 downto 0);
		signed	: in  std_logic;
		result	: out std_logic_vector(size-1 downto 0)
	);
end entity;
	
architecture behaviour of left_shifter is
	type BLOCK_TYPE is array (0 to size-1) of std_logic_vector(size-1 downto 0);
	signal all_results : BLOCK_TYPE;
begin
	process(data, shift) begin
		for i in 0 to size-1 loop
			all_results(i)(size-1 downto i) <= data(size-1-i downto 0);
			all_results(i)(i-1 downto 0) <= (others => '0');
		end loop;
		
		if (conv_integer(shift) < size) then
			result <= all_results(conv_integer(shift));
		else
			result <= (others => '0');
		end if;
	end process;
end architecture;